The Solid State Electronics group

The Solid State Electronics group at Liverpool University comprises of 7 academic and technical staff together with over 20 postgraduate and research assistants, led by Professor Bill Eccleston. The group has been active for about thirty years and has worked on a broad range of semiconductor devices and technology. Silicon device work has involved troubleshooting of anomalies on production devices but recently has been mostly concerned with full design, simulation, realisation and characterisation of novel devices. These have been fabricated at the Southampton University EPSRC Central Facility and also by GEC Plessey Semiconductors (now Mitel Semiconductor). Recent devices realised have been first generation, mesa isolated, vertical MOSFETs featuring SiGe source engineering, SiGe channel MOSFETs featuring low temperature plasma anodised gate oxides and SiGe HBT’s on bonded wafer SOI substrates. Pioneering work on low temperature oxidation of silicon using r.f. plasma has underpinned a major activity concerned with characterisation and reliability studies on gate oxides and silicon-on-insulator (SOI) dielectrics, in collaboration with major U.K Companies. More recently, group activities have extended into the areas of micro-machining and micro-systems, the use of SOI for low power CMOS circuit technology (PowerPack Consortium), poly-Si thin-film transistors for flat panel display application and semiconducting polymers for the same application. The group has a wide range of semiconductor device characterisation techniques in-house: d.c. parameter analysers inc. heated chuck and liquid nitrogen cryostat, variable freq. C-V etc. In particular, there is an extensive suite of dielectric test facilities including avalanche injection, photo I-V, 3-level charge pumping and spin-dependent recombination (SDR). Scanning ellipsometryhas been recently commissioned. Simulation employs Silvaco, TMA and ISE tools on work station and high power PC platforms. Cadence is used for mask design. SEM, (limited) TEM and other materials characterisation can be available by agreement with the Materials Science Dept. A brand new suite of clean rooms (450 m2) has been commissioned this year.

Silicon-on-Insulator research has been conducted over the last 15 years. Our earlier work concerned materials characterisation and explanations for anomalous device characteristics in close collaboration with Plessey Research (now Mitel Semiconductor), a number of other UK companies and other Universities. Major contributions have included identification of selfheating in SOI and associated monitoring techniques, characterisation of SIMOX and oxidised porous Si with relevance to reliability issues, new measurement techniques for SOI materials assessment, particularly carrier lifetime.

The recent circuits centred work involves consideration of device types and logic family type when designing circuits; for instance, using pass-gate transistor logic in arithmetic circuits which brings a packing density advantage and also reduced power consumption (less capacitance). Single pass transistors are very effective in SOI technology due to the reduced body effect and ease of producing dynamic threshold devices. We have designed 16-bit, selftimed adder demonstrator circuits which incorporate a number of logic circuit variants: some incorporate pass-gates, we also have static and dynamic logic styles. The adder is a typical component of asynchronous circuit designs. Test chips have been fabricated by NMRC (Cork, Ireland) and are currently at the packaging stage with testing scheduled over the summer (2001). A new project currently being planned, will build on this design work, first porting the designs to smaller geometry (0.25um) for which tools are available. We are using fully depleted devices at present but could adapt our designs quite easily for partially depleted. We would be interested in the judicious placement of gate-tied-to-body devices at strategic points in the circuit to take advantage of the low on-Vt. We hope to use bonded wafer SOI substrates which could incorporate ground planes under the BOX to suppress short IST-1-506653-CA (EUROSOI) - Annex I, vers. 6 (8/10/2003) - Approved by EC on 17/11/2003 106 of 126 channel effects due to drain field encroachment via the BOX. Our growing expertise is at the interface of device physics and gate level circuit design.

Key people

Steve Hall has recently been promoted to Professor in the Department of Electrical Engineering & Electronics at the University of Liverpool, U.K. He has research interests over a wide range of silicon devices and technology encompassing bipolar and MOS transistors together with associated materials and dielectric characterisation. He has been principal investigator of over 10 relevant projects funded by UK funding bodies EPSRC & MoD, all with strong, formal academic and industrial collaboration. He was principal investigator on projects which have successfully realised vertical 0.1 um channel vertical MOSFET, SiGe channel MOSFET devices and SiGe HBT’s on SOI. He is currently involved in collaborative projects with Mitel Semiconductor, concerned with low power CMOS and high frequency HBT. He manages work package WP4 concerned with vertical MOSFETs in the European Union funded ‘SIGMOS’ project. The overall aim of the SIGMOS project is to search for novel solutions to fundamental problems of CMOS channel and source/drain engineering. SiGe and SiGeC materials are applied to CMOS devices, with the aim of obtaining improved device performance. New device architectures will be explored, which extract maximum benefit from these new materials; these will include elevated SiGe sources and drains and vertical channels. The SIGMOS project is linked to the EURACCESS initiative, which aims to provide access to state of the art silicon processing facilities to researchers throughout Europe. The aim is to transfer technology from the University groups to the EURACCESS facility (LETI) to allow fabrication of 50nm SiGe PMOS transistors and 50nm SiGeC NMOS transistors with elevated SiGe sources and drains. Vertical MOS test devices will be fabricated at the Southampton Central Facility, UK.

Dr S.Taylor is a Reader in the Department of Electrical Engineering and Electronics at Liverpool University. His PhD thesis was concerned with the inductively coupled plasma oxidation of silicon. He has since then published over 100 papers in refereed journals and conferences in the field of silicon microelectronics, specialising in Si-SiO2 interface physics. He is currently Chairman of the UK Dielectrics Club and former member of the Program Committee of IEEE Semiconductor Interface Specialist Conference (SISC). He is currently researching into degradation mechanisms in submicron silicon MOSFETs and seeking to provide experimental results to be used in the formulation of a Monte Carlo based reliability simulator. Devices for this work have been provided by MITEL Semiconductor (Roborough Dr. Octavian Buiu has just been appointed lecturer in the department (July 2001). He has particular interests in the use of SOI substrates for building up intelligent sensors. His expertise covers materials and technologies for micro-electromechanical systems (MEMS), reliability of electronic devices and failure analysis, development and characterisation of low temperature processes for thin dielectric films, SOI (more precisely, SIMOX) characterisation by scanning ellipsometry.

Mr. David Donaghy is a Research Assistant at Liverpool University. His interest in SOI began with investigating SOI OP-Amps for a Masters thesis in 1995. Since then he has worked as an analogue IC engineer for 1½ years (1995-1997) for GEC Plessey Semiconductors concentrating on the optimisation and simulation properties of passive components as well as doing analogue layout. For the last 4 years, he has been investigating and designing SOI asynchronous adder circuits as part of Ph.D studies, which is in preparation. The circuits have been simulated using Fossum’s University of Florida model on a Hspice platform. Several papers have been published on the work so far. At present he is working on the EU funded SIGMOS project, investigating a novel 50nm vertical channel MOSFET structure. Parasitic capacitances of the structure and the effect that each of them has in a circuit environment is being investigated. David has 7 years experience in Cadence software and is heavily involved in the teaching of IC design to final year undergraduate students in the department.