|
|
||
|
|
|||
EUROSOI VIRTUAL JOURNAL
Title: Advanced SOI CMOS transistor technology for high performance microprocessors
Autors: Horstmann M, Wiatr M, Wei A, Hoentschel J, Feudel T, Scheiper T, Stephan R, Gerhadt M, Krugel S, Raab MTHEME: Device physics, modelling and simulation
Publication: SOLID-STATE ELECTRONICS
YEAR: 2009 MONTH: DEC
ISI Document Solution number: 534PS 10.1016/j.sse.2009.09.031
ABSTRACT: In this paper we present an overview of partially depleted Silicon on Insulator (PD SOI) CMOS transistor technologies for high performance microprocessors. To achieve a "high performance per watt" figure of merit, transistor technology elements like PD SOI, strained Si, aggressive junction scaling, asymmetric devices need hand-in-hand development with multiple core- and power-efficient designs. These techniques have been developed, applied and optimized for 45 nm SOI volume manufacturing at GLOBAL-FOUNDRIES in Dresden. To enable further transistor scaling to 32 nm design rules, High K Metal Gate (HKMG) technology is the key, Different HKMG integrations as well as future strained Si technologies, like strained silicon directly bonded on 501, and embedded Si:C are discussed
|
|
|---|
|
EUROSOI 2011 Granada |
|
EUROSOI 2010 Grenoble |
|
EUROSOI 2009 Chalmers |
|
EUROSOI 2008 Cork |
|
EUROSOI 2007 Leuven |
|
EUROSOI 2006 Grenoble |
|
EUROSOI 2005 Granada |
Pages viewed: 35640
Current Web Administrator: José Luis Padilla
.:: This web site is valid CSS and valid XHTML 1.1 ::.
Recommended screen resolution of 1024x768 or higher
