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EUROSOI VIRTUAL JOURNAL
Title: SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-Gate CMOS Insensitive to Process Variations and Transistor Mismatch
Autors: Nasalski P, Makosiej A, Giraud B, Vladimirescu A, Amara ATHEME: Device physics, modelling and simulation
Publication: ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
YEAR: 2009 MONTH: MAY
ISI Document Solution number: BNZ33 978-1-4244-3827-3
ABSTRACT: This paper presents a comparative study of two novel sub-32nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10-15% increase in speed and have a 2.5 to 5 times larger tolerance to V-th and L mismatch compared to published DG SAs. Both architectures take advantage of the back gate in order to improve circuit properties. The new CSA is 12% faster and reduces power consumption 3.3 times compared to the new VSA, with the latter having a significant advantage in size.
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